SEM EDS Analysis of Interconnecting Layers of a Bulk 7 nm Process FinFET

Integrated circuit (IC) chips are routinely investigated using EDS during both development and manufacturing, especially in failure and metal contamination analyses.

Here we present the SEM EDS analysis of the different layers of an IC chip (bulk sample) with, from bottom to top: FEOL (front-end-of-line), MOL and BEOL (middle- and back-end-of-line) layers.

The EDS maps acquired at 5 kV resolved fine features of Cobalt as small as 10 nm. Challenging elemental overlaps in the EDS map, like Cobalt-Copper and Silicon-Tungsten-Hafnium, are automatically deconvoluted using Bruker's ESPRIT software. The delayering of the sample was performed using plasma FIB.

Bruker's XFlash 7^® EDS Detector acquires high-resolution elemental maps with a high count rate and a low probe current, meaning semiconductor analysis can be carried out both faster and with high reliability. This is of particular benefit to those working in semiconductor R&D and failure analysis.

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Elemental distribution of different layers of an IC chip from BEOL (top) to FEOL (bottom) identified by SEM EDS. Overlapping elements like Co-Cu and Si-W-Hf are automatically deconvoluted.

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Elemental composition of an IC chip: SE image and individual elemental maps acquired by SEM EDS on a bulk sample. The delayering was done using a plasma FIB.

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